1. Field of the Invention
This invention relates generally to a method and apparatus for high density electronic packaging and, more particularly, to a method and apparatus adapted to process multiple 3-dimensional semiconductor devices at a single time.
2. Discussion of the Related Art
In semiconductor packaging applications, stacks of individual semiconductor chips or die are joined together to form a 3-dimensional device referred to as a cube. A method for fabricating cubes or modules including uniformly stacked, aligned circuit carrying layers is disclosed, for example in U.S. Pat. No. 4,617,160, issued to Belanger et al. on Oct. 14, 1986.
A first phase of cube processing is performed while the semiconductor chips are still in wafer form. During the first phase, input/output (I/O) leads are brought from an active area of the die to the kerf region using, for example, a thin film transfer wiring level. The die are then separated by dicing. The act of dicing exposes the thin film wire I/O on a corresponding edge of each die. During a second phase of cube processing, a 3-dimensional device or cube is formed by laminating a stack of the diced semiconductor chips together, back to front. A third phase of the cube processing is performed on one or more processing surfaces of a cube. The third phase of cube processing includes processing steps such as polishing, spin apply of an insulative layer, evaporation of a metalization layer, lithography and etching steps used to interconnect the transfer wire I/O's from one chip to the next for a particular cube.
In the present state of the art, cubes are processed individually one at a time. Each process step typically involves a special fixture, wherein an individual cube must be fitted into the special fixture. As a result, there are a multiplicity of different fixtures, one for each process step. Each cube must then be fixtured a multiplicity of times during the subsequent processing thereof. Extra handling care and process steps are needed when processing each cube individually. Furthermore, mechanically fixturing of individual cubes into a multi-up fixture is difficult, time consuming, and poses additional processing challenges. Still further, if different size cubes are processed due to the use of different size chips resulting from technology shrinks or the use of different technologies, then the tools may also have to be refitted with a new set of fixtures. This further adds excessive cost to the fabrication of cubes.
Additionally, the present known fixtures suffer disadvantages. Because of cube to cube size variations, gaps on the order of as little as 25 .mu.m can occur between individual cubes and corresponding fixtures. Such gaps disadvantageously lead to formation of edge beads (e.g., resulting from a build up of spun-on materials) , cracking of the cube edges, and the occurrence of material undesirably filling the gaps and gluing the cube into the corresponding fixture.
More particularly, edge beads, corresponding to thick areas of polyimide and/or photoresist on the edge of a cube, build up during spinning even if only a small gap (25-100 .mu.m) exists between the fixture and cube edge. Cube to cube size variation is typically large enough to make such tight fixturing difficult to impossible. An edge bead disadvantageously interferes with the processing of the outer most leads on a cube face.
When grinding and polishing a cube face, the cube needs to be held securely so that no movement occurs, otherwise a nonplanar cube face will result. Similarly, gaps between the fixture and the cube can lead to movement of the cube and chipping of the silicon making up the cube. Thermal expansion differences between the cube and the fixture are also important. The silicon making up the cube can easily be cracked, chipped, or the cube can fall out of the fixture during processing if the thermal coefficient of expansion (TCE) of the fixture and of the cube are not comparable. Still, further, polyimides and photoresists can undesirably fill any gaps between the cube and fixture. Upon a subsequent thermal processing, those materials will cure, thus locking the cube into the fixture. Removing the cube from the fixture and cleaning the cube after each step is costly and further gives rise to additional handling damage. Thus during individual cube processing, there exists the potential for numerous problems associated with the use of many fixtures, individual cube handling, and inefficient fixtures.
In U.S. Pat. No. 4,999,311, a method of fabricating interconnections to I/O leads on layered electronic assemblies is disclosed. In the '311 patent, layered electronic assemblies are mechanically compressed together, wherein interconnect circuitry is formed on a selected face of several layered electronic assemblies simultaneously. The '311 patent however does not provide a surface for referencing the selected face of the electronic assemblies to be flat. In addition, the electronic assemblies of the '311 patent will also suffer from a tendency to shift around as the assemblies are mechanically compressed together, thus not providing for an accurate known positioning of individual assemblies for subsequent stepwise alignment during processing of individual assemblies.